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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX14569 dual-pair llt with charge pump and high-esd protection 19-5523; rev 0; 9/10 general description the MAX14569 is a dedicated dual-pair unidirectional logic-level translator that is ideal for industrial and meter- ing applications. voltages v cc and v l set the logic levels on either side of the device. logic-high signals present on the v l side of the device appear as high- voltage logic signals on the v cc side of the device and vice versa. the device has two pairs of logic-level translators in back-to-back configuration: one logic-level translator from a low voltage to a high voltage and the other logic- level translator from a high voltage to a low voltage. the device also features a high-efficiency charge pump to boost the battery input, v bat , to v cc (5v). the device features an extreme power-saving mode that reduces supply current to a typical 0.01 f a. the device also features thermal short-circuit protection for enhanced protection in applications that route signals externally. in addition, the device features enhanced high electro- static discharge (esd) human body model (hbm) pro- tection on outavcc, inbvcc, outcvcc, and indvcc ports up to q 25kv. the MAX14569 is available in a 16-pin qsop package, and is specified over the -40 nc to +85 n c extended temperature range. features s ultra-low shutdown supply current, 0.01a (typ) s ultra-low v l supply current, 1a (max) s operates down to 1.6v on v l s continuous current drive capability > 10ma s extended esd protection on v cc input and output lines 25kv human body model 15kv iec 61000-4-2 air-gap discharge 12kv iec 61000-4-2 contact discharge s 16-pin qsop package s -40n c to +85n c extended operating temperature range applications automatic meter reader remote communications system industrial networking ordering information + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. typical operating circuit processor 0.1f 1f 2.2f 0.47f 1.8v to 3.3v lithium battery v cc 5v cp2 cp1 v l v bat charge pump gnd gnd enab en inavl data outbvl data outavcc inbvcc meter transmitter unit gnd meter transmitter unit gnd encd en incvl data outdvl data outcvcc indvcc MAX14569 part temp range pin-package MAX14569eee+t -40n c to +85nc 16 qsop
MAX14569 dual-pair llt with charge pump and high-esd protection 2 (all voltages referenced to gnd.) v bat , v l .................................................................. -0.3v to +6v v cc (no shutdown condition) ..................... (v bat - 0.3v) to +6v v cc (shutdown condition) ....................................... -0.3v to +6v cp1 .......................................................... -0.3v to (v bat + 0.3v) cp2 .......................................................................... -0.3v to +6v enab, encd ........................................................... -0.3v to +6v inavl, incvl .......................................................... -0.3v to +6v outbvl, outdvl ...................................... -0.3v to (v l + 0.3v) inbvcc, indvcc .................................... -0.3v to (v cc + 0.3v) outavcc, outcvcc ............................. -0.3v to (v cc + 0.3v) short-circuit current outavcc, outcvcc, outbvl, outdvl to gnd ................ continuous short-circuit duration outavcc, outcvcc, outbvl, outdvl to gnd .................................... continuous continuous power dissipation (t a = +70 n c) qsop (derate 9.6mw/ n c above +70 n c) .................. 771.5mw junction-to-ambient thermal resistance (note 1) b ja ........................................................................... 103.7 n c/w junction-to-case thermal resistance (note 1) b jc ............................................................................... 37 n c/w operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -65 n c to +150 n c junction temperature ..................................................... +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v bat = 2.3v to 5.5v, v l = 1.6v to 5.5v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v bat = 3.6v, v l = 3.0v, and t a = +25 n c.) (notes 2, 3, 4) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units power supplies v bat supply range v bat 2.3 5.5 v v l supply range v l 1.6 5.5 v supply current from v l i qvl inbvcc = indvcc = v cc , inavl = incvl = v l 1 f a v bat shutdown supply current i shdn-vbat v inavl = v incvl = 0v, v enab = v encd = 0v 0.01 0.5 f a v l shutdown supply current i shdn-vl v enab = v encd = 0v 0.01 0.5 f a v bat change in supply current with enab and encd at v il d i vbat v enab = v encd = v il (notes 2, 4, 5) 1 f a outavcc shutdown mode leakage current i outavcc_leak v enab = 0v, v encd = v ih , v outavcc = 5v 0.01 1 f a outcvcc shutdown mode leakage current i outcvcc_leak v enab = v ih , v encd = 0v, v outcvcc = 5v 0.01 1 f a outbvl, outdvl shutdown mode leakage current i outbvl_leak i outdvl_leak v enab = v encd = 0v, v outbvl = v outdvl = 0v 0.01 1 f a inbvcc shutdown mode leakage current i inbvcc_leak v enab = 0v, v encd = v ih , v inbvcc = 5v 0.01 1 f a indvcc shutdown mode leakage current i indvcc_leak v enab = v ih , v encd = 0v, v indvcc = 5v 0.01 1 f a
MAX14569 dual-pair llt with charge pump and high-esd protection 3 electrical characteristics (continued) (v bat = 2.3v to 5.5v, v l = 1.6v to 5.5v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v bat = 3.6v, v l = 3.0v, and t a = +25 n c.) (notes 2, 3, 4) parameter symbol conditions min typ max units inavl, incvl leakage current i inavl_leak i incvl_leak v inavl = v incvl = v l 0.01 1 f a enab, encd input leakage current i enab_leak i encd_leak v enab = v encd = 5v 0.01 1 f a outavcc, outcvcc short-circuit output current i sh v outavcc = 0v or v outcvcc = 0v, v bat r 2.7v 100 250 ma logic levels inavl, incvl input- voltage high v ihl 0.7 x v l v inavl, incvl input- voltage low v ill 0.3 x v l v inbvcc, indvcc input- voltage high v ihc 0.7 x v cc v inbvcc, indvcc input- voltage low v ilc 0.3 x v cc v enab, encd input- voltage high v ih 1.2 v enab, encd input- voltage low v il 0.4 v enab, encd input- voltage hysteresis v hys 120 mv outbvl, outdvl output-voltage high v ohl outbvl or outdvl source current = 100 f a, inbvcc or indvcc > v ihc v l - 0.1 v outbvl or outdvl source current = 4ma, inbvcc or indvcc > v ihc v l - 0.4 outbvl, outdvl output-voltage low v oll outbvl or outdvl sink current = 100 f a, inbvcc or indvcc < v ilc 0.1 v outbvl or outdvl sink current = 4ma, inbvcc or indvcc < v ilc 0.4 outavcc, outcvcc output-voltage high v ohc outavcc or outcvcc source current = 100 f a, inavl or incvl > v ihl , 2.7v p v bat p 4.5v 4.6 v outavcc or outcvcc source current = 20ma, inavl or incvl > v ihl, 2.7v p v bat p 4.5v 4.3
MAX14569 dual-pair llt with charge pump and high-esd protection 4 electrical characteristics (continued) (v bat = 2.3v to 5.5v, v l = 1.6v to 5.5v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v bat = 3.6v, v l = 3.0v, and t a = +25 n c.) (notes 2, 3, 4) parameter symbol conditions min typ max units outavcc, outcvcc output-voltage low v olc outavcc or outcvcc sink current = 100 f a, inavl or incvl < v ill, 2.7v p v bat p 4.5v 0.1 v outavcc or outcvcc sink current = 20ma, inavl or incvl < v ill, 2.7v p v bat p 4.5v 0.4 timing characteristics (note 6) outavcc, outcvcc rise time t rvcc figure 1 25 ns outavcc, outcvcc fall time t fvcc figure 1 25 ns outbvl, outdvl rise time t rvl figure 2 25 ns outbvl, outdvl fall time t fvl figure 2 25 ns propagation delay (driving inavl, incvl) low-to-high t pvl-vcc-lh figure 1 30 ns propagation delay (driving inavl, incvl) high-to-low t pvl-vcc-hl figure 1 30 ns propagation delay (driving inbvcc, indvcc) low-to-high t pvcc-vl-lh figure 2 30 ns propagation delay (driving inbvcc, indvcc) high-to-low t pvcc-vl-hl figure 2 30 ns maximum data rate 12 mbps charge pump v cc output voltage v cc i cc = 10ma, 2.7v p v bat p 4.5v 4.7 5.0 5.3 v i cc = 40ma, 3.0v p v bat p 4.5v 4.7 5.0 5.3 v cc output voltage ripple i cc = 40ma 45 mv p-p v cc line regulation i cc = 10ma, 2.7v p v bat p 4.5v -1 +1 % v cc load regulation d v cc 0 p i cc p 40ma, v bat = 3.6v -1 % quiescent current i q i cc = 0ma, v bat = 3.6v 200 f a cp_ leakage current i cp_leak v bat = 3.6v, v cc = 0v v enab = v encd = 0v 0.01 0.5 f a
MAX14569 dual-pair llt with charge pump and high-esd protection 5 note 2: v l must be less than or equal to v cc during normal operation. however, v l can be greater than v cc during startup and shutdown conditions. note 3: all units are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and not production tested. note 4: connect a 0.47f capacitor between cp1 and cp2. note 5: d i vbat = [i vbat (v enab = v encd = v il ) - i vbat (v enab = v encd = 0v)]. guaranteed by design and not production tested. note 6: v cc = 5.0v, v l = 1.6v to v cc , v bat = 2.7v to 3.6v, v enab = v encd > v ih , r s = 50 i , r l = 1m i , c l = 15pf, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v bat = 3.6v, v l = 3.0v, and t a = +25 n c. electrical characteristics (continued) (v bat = 2.3v to 5.5v, v l = 1.6v to 5.5v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v bat = 3.6v, v l = 3.0v, and t a = +25 n c.) (notes 2, 3, 4) parameter symbol conditions min typ max units cp_ switching frequency f cp no capacitor between cp1 and cp2, 2.7v p v bat p 4.5v 0.5 1 1.5 mhz efficiency e i cc = 10ma, v bat = 2.7v, v cc = 5.0v 90 % thermal protection thermal shutdown t shdn +150 n c thermal hysteresis t hyst +20 n c esd protection outavcc, inbvcc, outcvcc, indvcc human body model 25 kv iec 61000-4-2 air gap discharge 15 iec 61000-4-2 contact discharge 12 all other pins human body model 2 kv
MAX14569 dual-pair llt with charge pump and high-esd protection 6 figure 1. push-pull driving inavl/incvl test circuit and timing figure 2. push-pull driving inbvcc/indvcc test circuit and timing v l v cc v l c l r l v bat inavl / incvl 50i out avc c/ outcvcc outavcc/ outcvcc t rvcc t pvl-vcc-lh t pvl-vcc-hl 90% 90% t fvcc inavl/ incvl 50% 50% 50% 10% 50% 10% MAX14569 v cc v l v l c l r l v bat inbvcc/ indvcc 50i outbvl/ outdvl inbvcc/ indvcc outbvl/ outdvl t pvcc-vl-lh t pvcc-vl-hl t rvl t fvl 10% 10% 50% 90% 50% 50% 50% 90% MAX14569
MAX14569 dual-pair llt with charge pump and high-esd protection 7 typical operating characteristics (v bat = 3.6v, v l = 3v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, connect 0.47 f f capacitor between cp1 and cp2, data rate = 1mbps, t a = +25 n c, unless otherwise noted.) i cc (ma) v cc output voltage ripple (mv p-p ) 35 30 20 25 10 15 5 0 40 output ripple vs. load current MAX14569 toc09 20 40 60 80 100 120 140 160 180 200 0 enab = encd = high v bat = 3.6v cp_ load regulation (v cc vs. i cc ) MAX14569 toc08 i cc (ma) v cc (v) 35 30 25 20 15 10 5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 4.5 0 40 enab = encd = high cp_ line regulation (v cc vs. v bat ) MAX14569 toc07 v bat (v) v cc (v) 4.2 3.9 3.6 3.3 3.0 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 4.90 2.7 4.5 enab = encd = high i cc = 10ma v cc short-circuit current vs. v bat MAX14569 toc06 v bat (v) i sh (ma) 4.1 3.2 100 200 300 400 500 600 700 800 900 1000 0 2.3 5.0 t a = 85c t a = 25c outavcc/outcvcc short-to-ground t a = -40c cp_ operating frequency vs. v bat MAX14569 toc05 v bat (v) cp_ operating frequency (khz) 4.1 3.2 910 920 930 940 950 960 970 980 990 1000 900 2.3 5.0 t a = 85c t a = 25c t a = -40c v l shutdown supply current vs. temperature MAX14569 toc04 temperature (c) v l shutdown supply current (na) 60 35 -15 10 0.1 0.2 0.3 0.4 0.6 0.5 0.7 0.8 0 -40 85 v enab = v encd = 0v v l = 1.8v v l = 2.7v v l = 3.3v v l shutdown supply current vs. v l voltage MAX14569 toc03 v l voltage (v) v l shutdown supply current (na) 3.1 2.6 2.1 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 1.6 3.6 v enab = v encd = 0v v bat shutdown supply current vs. temperature MAX14569 toc02 temperature ( c) v bat shutdown supply current (na) 60 35 10 v bat = 4.5v -15 1 2 3 4 5 6 7 8 9 10 0 -40 85 v enab = v encd = 0v v inavl = v incvl = 0v v bat = 2.7v v bat = 3.6v v bat shutdown supply current vs. v bat voltage MAX14569 toc01 v bat voltage (v) v bat shutdown supply current (na) 4.7 3.9 3.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 2.3 5.5 v enab = v encd = 0v v inavl = v incvl = 0v
MAX14569 dual-pair llt with charge pump and high-esd protection 8 typical operating characteristics (continued) (v bat = 3.6v, v l = 3v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, connect 0.47 f f capacitor between cp1 and cp2, data rate = 1mbps, t a = +25 n c, unless otherwise noted.) outavcc/outcvcc propagation delay vs. load capacitance MAX14569 toc15 load capacitance (pf) outavcc/outcvcc propagation delay (ns) 800 600 400 200 10 20 30 40 t pvl-vcc-lh t pvl-vcc-hl 50 60 70 80 90 100 0 0 1000 outavcc/outcvcc rise time vs. load capacitance MAX14569 toc14 load capacitance (pf) outavcc/outcvcc rise time (ns) 800 600 400 200 10 20 30 40 50 60 70 80 90 100 0 0 1000 outavcc/outcvcc fall time vs. load capacitance MAX14569 toc13 load capacitance (pf) outavcc/outcvcc fall time (ns) 800 600 400 200 10 20 30 40 50 60 70 80 90 100 0 0 1000 outbv l/ outdvl propagation delay vs. load capacitance MAX14569 toc12 load capacitance (pf) outbv l/ outdvl propagation delay (ns) 80 60 40 20 1 2 3 4 5 6 t pvcc-vl-lh 7 8 9 10 0 0 100 t pvcc-vl-hl outbv l/ outdvl rise time vs. load capacitance MAX14569 toc11 load capacitance (pf) outbvl/outdvl rise time (ns) 80 60 40 20 1 2 3 4 5 6 7 8 9 10 0 0 100 outbv l/ outdvl fall time vs. load capacitance MAX14569 toc10 load capacitance (pf) outbvl/outdvl fall time (ns) 80 60 40 20 1 2 3 4 5 6 7 8 9 10 0 0 100
MAX14569 dual-pair llt with charge pump and high-esd protection 9 typical operating characteristics (continued) (v bat = 3.6v, v l = 3v, c vbat = 1 f f, c vcc = 2.2 f f, c vl = 0.1 f f, connect 0.47 f f capacitor between cp1 and cp2, data rate = 1mbps, t a = +25 n c, unless otherwise noted.) driving inbvcc/indvcc MAX14569 toc19 out_vl 2v/div in_vcc 2v/div 400ns/div c outbvl /c outdvl = 15pf driving inavl/incvl MAX14569 toc18 out_v cc 2v/div in_vl 2v/div 400ns/div c outavcc /c outcvcc = 1000pf driving inavl/incvl MAX14569 toc17 out_v cc 2v/div in_vl 2v/div 400ns/div c outavcc /c outcvcc = 150pf driving inavl/incvl MAX14569 toc16 out_v cc 2v/div in_vl 2v/div c outavcc /c outcvcc = 15pf 400ns/div
MAX14569 dual-pair llt with charge pump and high-esd protection 10 pin configuration pin description 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 cp1 v bat cp2 v cc outavcc inbvcc outcvcc indvcc top view qsop enab v l encd incvl inavl outbvl outdvl gnd + MAX14569 pin name function 1 v l logic supply voltage, +1.6v to +5.5v. bypass v l to gnd with a 0.1 f f capacitor placed as close as possible to the device. 2 enab enable input for a and b ports. drive enab low for shutdown mode, or drive enab high for normal operation. 3 encd enable input for c and d ports. drive encd low for shutdown mode, or drive encd high for normal operation. 4 inavl input a port. referenced to v l . 5 outbvl output b port. referenced to v l . 6 incvl input c port. referenced to v l . 7 outdvl output d port. referenced to v l . 8 gnd ground 9 indvcc input d port. referenced to v cc . 10 outcvcc output c port. referenced to v cc . 11 inbvcc input b port. referenced to v cc . 12 outavcc output a port. referenced to v cc . 13 v cc charge-pump output. bypass v cc to gnd with a 2.2 f f ceramic capacitor placed as close as possible to the v cc pin to have high esd protection on outavcc, inbvcc, outcvcc, and indvcc pins. 14 cp2 external charge-pump capacitor connection 15 v bat battery input, +2.3v to +5.5v. bypass v bat to gnd with a 1 f f capacitor placed as close as possible to the device. 16 cp1 external charge-pump capacitor connection
MAX14569 dual-pair llt with charge pump and high-esd protection 11 detailed description the MAX14569 is a dedicated dual-pair unidirectional logic-level translator that is ideal for automatic remote- metering applications. externally applied voltage v l and regulated output voltage v cc set the logic levels on either side of the device. the device boosts the v bat supply input voltage to a charge-pump-regulated output, v cc . logic-high signals present on the v l side of the device appear as a high- voltage logic signals on the v cc side of the device and vice versa. the device has two pairs of logic-level translators in back-to-back configuration: one logic-level translator from a low voltage to a high voltage and the other logic- level translator from a high voltage to a low voltage. the device features an extreme power-saving mode that reduces supply current to a typical 0.01 f a. the device also features thermal short-circuit protection on the v cc side for enhanced protection in applications that route signals externally. level translation for proper operation, ensure that 2.3v p v bat p 5.5v, 1.6v p v l p 5.5v. the device enters low-power shutdown mode when enab = encd = gnd (see the functional table ). in shutdown mode, the inavl, inbvcc, incvl, indvcc, outavcc and outcvcc are in high-imped - ance mode and the outbvl and outdvl are pulled down to gnd. the maximum data rate depends heavily on the load capacitance (see the rise/fall times in the typical operating characteristics ), output impedance of the driver, and the operating voltage range. output load requirements the device is designed to drive a wide variety of load types including a high capacitive load. to protect the v cc outputs (outavcc, outcvcc) from a harsh external environment, the v cc outputs are ruggedized with a high esd-capable output structure. when the high capacitive load is connected to the v cc output side, the current is limited by the charge-pump circuit along with the output driver impedance. the device is also pro - tected by the thermal protection. functional diagram functional table v l v cc v l v bat outdvl indvcc gnd v l v l v cc incvl encd enab outcvcc v l v cc outbvl inbvcc v cc inavl outavcc v cc charge pump MAX14569 inputs drivers output events enab encd low low device is in shutdown outavcc, outcvcc: high impedance outbvl, outdvl: pulldown to gnd low high outavcc: high impedance outbvl: pulldown to gnd incvl to outcvcc indvcc to outdvl high low inavl to outavcc inbvcc to outbvl outcvcc: high impedance outdvl: pulldown to gnd high high inavl to outavcc inbvcc to outbvl incvl to outcvcc indvcc to outdvl
MAX14569 dual-pair llt with charge pump and high-esd protection 12 shutdown mode the device features two enable inputs (enab, encd) that place the device into a low-power shutdown mode when both are driven low. if either enab or encd is pulled high, the internal charge pump starts working and generates 5v on v cc . when both enab and encd are driven low, the MAX14569 enters shutdown mode and draws a minimum current from v l and v bat . to minimize supply current in shutdown mode, connect inavl and incvl to ground. charge pump the internal charge pump provides 5v on v cc when v bat is between 2.7v and 4.5v. when v bat is between 2.3v and 2.7v, v cc is twice the voltage of v bat . the output is regulated to 5v as long as the battery voltage supports it. thermal protection the device features thermal shutdown function neces - sary to protect the device. when the junction tempera - ture exceeds +150 n c (typ), the charge pump turns off and outavcc, outbvl, outcvcc, outdvl are low. this limits the device temperature from rising further. when the temperature drops 20 n c (typ) below +150 n c (typ), the device resumes normal operation. applications information layout recommendations use standard high-speed layout practices when laying out a board with the device. for example, to minimize line coupling, place all other signal lines not connected to the device at least 1x the substrate height of the pcb away from the input and output lines of the device. power-supply decoupling to reduce ripple and the chance of introducing data errors, bypass v l to ground with a 0.1 f f ceramic capac - itor, v bat to ground with a 1 f f ceramic capacitor, and v cc to ground with a 2.2 f f ceramic capacitor. place all capacitors as close as possible to the power-supply inputs. 25kv esd protection as with all maxim devices, esd protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assem - bly. the outavcc, inbvcc, outcvcc, indvcc pins have extra protection against static electricity. maxims engineers have developed state-of-the-art structures to protect these pins against esd of q 25kv without dam - age. the esd structures withstand high esd in all states: normal operation, shutdown, and powered down. after an esd event, the device keeps working without latchup or damage. esd protection can be tested in various ways. the outavcc, inbvcc, outcvcc, and indvcc pins are characterized for protection to the following limits: u q 25kv using the human body model u q 15kv using the air-gap discharge method specified in iec 61000-4-2 u q 12kv using the contact discharge method specified in iec 61000-4-2 esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 3 shows the human body model, and figure 4 shows the current waveform it generates when dis - charged into a low-impedance state. this model consists of a 100pf capacitor charged to the esd voltage of inter - est, which is then discharged into the test device through a 1.5k i resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment. it does not spe - cifically refer to integrated circuits. the major difference between tests done using the human body model and iec 61000-4-2 is higher peak current in iec 61000-4-2, because series resistance is lower in the iec 61000-4-2 model. hence, the esd withstand voltage measured to iec 61000-4-2 is generally lower than that measured using the human body model. figure 5 shows the iec 61000-4-2 model, and figure 6 shows the curre nt wave - form for the q 8kv, iec 61000-4-2, level 4, esd contact discharge method.
MAX14569 dual-pair llt with charge pump and high-esd protection 13 chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. figure 3. human body esd test model figure 5. iec 61000-4-2 esd test model figure 4. human body current waveform figure 6. iec 61000-4-2 esd generator current waveform charge-current limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1500 high- voltage dc source device under test i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes charge current limit resistor discharge resistance storage capacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test t r = 0.7ns to 1ns 30n s 60n s t 100% 90% 10% i peak i package type package code outline no. land pattern no. 16 qsop e16+4 21-0055 90-0167
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX14569 dual-pair llt with charge pump and high-esd protection revision history revision number revision date description pages changed 0 9/10 initial release

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